Field of the Invention
The present invention relates to an elastic membrane for use in a substrate holding apparatus for holding a substrate such as a semiconductor wafer and pressing the substrate against a polishing surface in a polishing apparatus for polishing and planarizing the substrate. Further, the present invention relates to a substrate holding apparatus having such elastic membrane.
Description of the Related Art
In recent years, high integration and high density in semiconductor device demands smaller and smaller wiring patterns or interconnections and also more and more interconnection layers. Multilayer interconnections in smaller circuits result in greater steps which reflect surface irregularities on lower interconnection layers. An increase in the number of interconnection layers makes film coating performance (step coverage) poor over stepped configurations of thin films. Therefore, better multilayer interconnections need to have the improved step coverage and proper surface planarization. Further, since the depth of focus of a photolithographic optical system is smaller with miniaturization of a photolithographic process, a surface of the semiconductor device needs to be planarized such that irregular steps on the surface of the semiconductor device will fall within the depth of focus.
Thus, in a manufacturing process of a semiconductor device, it increasingly becomes important to planarize a surface of the semiconductor device. One of the most important planarizing technologies is chemical mechanical polishing (CMP). In the chemical mechanical polishing, while a polishing liquid containing abrasive particles such as silica (SiO2) therein is supplied onto a polishing surface such as a polishing pad, a substrate such as a semiconductor wafer is brought into sliding contact with the polishing surface and polished using the polishing apparatus.
This kind of polishing apparatus includes a polishing table having a polishing surface formed by a polishing pad, and a substrate holding apparatus for holding a substrate such as a semiconductor wafer. When the semiconductor wafer is polished with such a polishing apparatus, the semiconductor wafer is held and pressed against the polishing surface under a predetermined pressure by the substrate holding apparatus. At this time, the polishing table and the substrate holding apparatus are moved relative to each other to bring the semiconductor wafer into sliding contact with the polishing surface, so that the surface of the semiconductor wafer is polished to a flat mirror finish.
In such polishing apparatus, if a polishing rate of the semiconductor wafer is not uniform over the entire surface of the semiconductor wafer, then the semiconductor wafer is insufficiently or excessively polished depending on the polishing rate of each area of the semiconductor wafer. Therefore, there has been known a polishing apparatus in which a plurality of concentric pressure chambers defined by an elastic membrane are provided at a lower portion of the substrate holding apparatus, and by controlling pressures of pressurized fluid supplied to the respective pressure chambers, the semiconductor wafer is pressed against the polishing surface under different pressures at respective pressurizing areas, along a radial direction of the semiconductor wafer, corresponding to the respective pressure chambers.
FIG. 1 shows an example of a substrate holding apparatus of the above polishing apparatus. As shown in FIG. 1, the substrate holding apparatus has an apparatus body 200, a retainer ring 202, and an elastic membrane 204 provided on a lower surface of the apparatus body 200. On an upper surface of the elastic membrane 204, a plurality of (four in the figure) concentric circumferential walls 204a, 204b, 204c and 204d are provided. By these concentric circumferential walls 204a, 204b, 204c and 204d, a circular central pressure chamber 206 located at a central part of the semiconductor wafer W, an annular edge pressure chamber 208 located at the outermost part of the semiconductor wafer W, and two annular intermediate pressure chambers 210, 212 located between the central pressure chamber 206 and the edge pressure chamber 208 are formed between the upper surface of the elastic membrane 204 and the lower surface of the apparatus body 200.
With this configuration, the semiconductor wafer W is held by the substrate holding apparatus in such a state that there are four divided pressurizing areas, on the elastic membrane 204, comprising a circular central pressurizing area CA corresponding to the central pressure chamber 206, an annular edge pressurizing area EA corresponding to the edge pressure chamber 208, and two annular intermediate pressurizing areas MA1, MA2 corresponding to the intermediate pressure chambers 210, 212.
In the apparatus body 200, a passage 214 communicating with the central pressure chamber 206, a passage 216 communicating with the edge pressure chamber 208, and passages 218, 220 communicating respectively with the intermediate pressure chambers 210, 212 are formed. The respective passages 214, 216, 218 and 220 are connected via respective passages 222, 224, 226 and 228 to a fluid supply source 230. Further, opening and closing valves V10, V11, V12 and V 13 and pressure regulators R10, R11, R12 and R13 are provided in the passages 222, 224, 226 and 228, respectively.
The respective pressure regulators R10, R11, R12 and R13 have pressure adjusting function for adjusting pressures of pressurized fluid to be supplied from the fluid supply source 230 to the respective pressure chambers 206, 208, 210 and 212. The pressure regulators R10, R11, R12 and R13 and the opening and closing valves V10, V11, V12 and V13 are connected to a controller 232, and operations of these pressure regulators and these valves are controlled by the controller 232.
With this arrangement, by controlling respective pressures of the pressurized fluid to be supplied to the respective pressure chambers 206, 208, 210 and 212 in such a state that the semiconductor wafer W is held by the substrate holding apparatus, the semiconductor wafer W can be pressed against the polishing surface (not shown) under different pressures at the respective pressurizing areas CA, EA, MA1 and MA2 on the elastic membrane 204 along a radial direction of the semiconductor wafer W.
In order to transmit the fluid pressures of the pressure chambers 206, 208, 210 and 212 defined on the upper surface of the elastic membrane 204 toward the semiconductor wafer W efficiently and to press the semiconductor wafer under a uniform pressure from the central part to the edge part of the semiconductor wafer W, a flexible material such as rubber is generally used for the elastic membrane 204.
In the case where a substrate such as a semiconductor wafer is held and pressed against the polishing surface to be polished by such substrate holding apparatus, if different pressures of the pressurized fluid are applied to two adjacent pressure chambers, then there occurs a step-like difference in pressing pressures (polishing pressures) for pressing the substrate in two adjacent pressurizing areas. As a result, a step-like height difference is produced also in polishing configuration (polishing profile). In this case, if there is a large pressure difference in pressures of the pressurized fluid supplied to the two adjacent pressure chambers, the step-like height difference in polishing configuration (polishing profile) becomes larger depending on the pressure difference in pressures for pressing the substrate in the two adjacent pressurizing areas.
Therefore, the applicant of the present invention has proposed to provide a diaphragm onto the elastic membrane so as to exist on both sides of the boundary between the two adjacent pressure chambers, the diaphragm being composed of a material having higher rigidity (large modulus of longitudinal elasticity) than the elastic membrane, as disclosed in Japanese laid-open patent publication No. 2009-131920.
FIG. 2 is a graph showing the relationship between locations along a radial direction of a semiconductor wafer and a polishing rate when the semiconductor wafer is held and polished by the substrate holding apparatus shown in FIG. 1, while the pressures of the pressurized fluid supplied to the respective pressure chambers 206, 208, 210 and 212 are equalized. As shown by a solid line A in FIG. 2, there are cases where the polishing rate is gradually decreased toward a radially outward direction of the semiconductor wafer. With respect to radial locations of the semiconductor wafer in FIG. 2, the areas CA, MA1 and MA2 along a radial direction of the semiconductor wafer correspond to respective pressurizing areas CA, MA1 and MA2 on the elastic membrane 204 shown in FIG. 1.
In such case, when the pressures of the pressurized fluid supplied to the intermediate pressure chambers 210, 212 are increased to increase the polishing rate in the areas of the semiconductor wafer corresponding to the intermediate pressurizing areas MA1, MA2, as shown by a dotted-dashed line B in FIG. 2, the polishing rate in the areas corresponding to the intermediate pressurizing areas MA1, MA2 is increased as a whole, but the inclination of the polishing rate in the intermediate pressurizing areas MA1, MA2 is substantially the same as the inclination of the polishing rate shown by the solid line A showing the case where the pressures of the pressurized fluid supplied to the intermediate pressure chambers 210, 212 are not increased. That is, the polishing rate in the intermediate pressurizing areas MA1, MA2 is increased in parallel at approximately the same rate while keeping the inclination of the polishing rate approximately constant.
Accordingly, the range of polishing rate distribution (variation range of polishing rate) over the entire surface of the semiconductor wafer is narrowed, however the range of polishing rate distribution (variation range of polishing rate) along a radial direction of the semiconductor wafer in the respective pressurizing areas, e.g. in the intermediate pressurizing area MA1, is not narrowed even when the pressure of the pressurized fluid is increased. Therefore, by the size of the radial area width of the pressurizing area MA1, the enhancement of uniformity of the surface, being polished, of the semiconductor wafer is hindered and the improvement of yield is limited.